1. Field of the Invention
This invention is directed to a method for forming silicide regions for low-resistance electrical connections to integrated devices formed on silicon substrates. The reduced contact resistances provide the devices with the capability to operate at relatively high speeds.
2. Description of the Related Art
Many techniques have been developed for forming silicide regions for integrated device contacts, particularly for metal-oxide-semiconductor (MOS) devices formed on silicon substrates. Most of these techniques involve the formation of a metal layer over gate, drain or source regions upon which the silicide is desired to be formed. These techniques then use thermal treatment for extended periods of time to react the metal with the silicon composing the gate, drain and/or source regions, to form the low-resistivity silicide regions. The substrate is further processed by removing the unreacted metal layer.
Techniques for forming silicides are subject to several stringent process constraints that must be met in order for such techniques to be effective. These constraints include: (1) the metal used to form the silicide and the temperature at which the silicide is formed must be carefully selected so that the metal diffuses into the silicon, to avoid the formation of leakage paths between the source, drain and gate of an integrated device; (2) for self-aligned silicidation techniques, the metal layer must not react with the insulating material composing the side walls of the gate; (3) the dopants must not segregate appreciably into the silicide regions so that low contact resistance can be achieved; (4) the technique should have a process window that allows the silicide region to be formed on both c-silicon and poly-silicon; (5) the silicide formation should be insensitive to dopants present in the silicon; and (6) the metal atoms should not diffuse beyond the silicide regions to prevent increase in junction leakage. The simultaneous achievement of all of the above-stated criteria is at best difficult for most conventional silicidation techniques, especially those that use relatively extensive thermal treatments. Most often, a failure to perform the conventional technique within its relatively narrow process margins manifests itself in the occurrence of defects due to thermal drift of the metal atoms beyond desired boundaries during the relatively prolonged thermal treatment periods required by such techniques. If the silicide region extends beyond its design dimensions, it can cause leakage paths between the gate, source/drain and the substrate. There is therefore a great need for a technique that enhances silicidation process margins beyond those conventionally available.
In addition to conventional techniques that use prolonged thermal treatments, some conventional silicidation techniques use ion implantation to achieve formation of the silicide regions. These ion-implantation silicidation techniques use either ion beam mixing of different ion types to produce a silicide of a desired composition, or implantation of a desired species of metal ions in a proportion needed to achieve proper stoichiometry. In either of these two types of techniques, the ion-implantation is so extensive as to be extremely time-consuming, especially if a stoichiometric proportion of ions needed to make the silicide must be implanted into the silicon substrate. In addition, extensive ion implantation will eventually lead to `knock-on`, a phenomenon in which moving ions strike ions previously implanted, driving them further than desired into the silicon substrate. The occurrence of knock-on leads to increased junction leakage. Thus, there is a significant need for a technique that can overcome the above-noted disadvantages of conventional silicidation techniques.
A constraint of the silicidation techniques discussed above is that the silicide thickness over the gate and the polysilicon runners is the same as that over the source/drain regions. As source/drain junctions are scaled to shallower depths, the silicide thickness over the source/drain also needs to be lowered to prevent leakage. However, silicide thickness scaling is not necessary over the gate region and it is in fact advantageous to have thicker silicide over the gate than the source/drain. Such a silicide can be formed either by depositing a thicker metal layer over the gate than the source/drain, or by subjecting the gate to a higher thermal budget. Neither of these two options are feasible using conventional silicide formation techniques.